Field of the Invention
The present invention relates to an address transition detector of a semiconductor memory device, and more particularly to an address transition detector capable of accurately producing data even for long address transition times.
Usually, an address transition detector (hereinafter referred to as the ATD) is used in a device such as a static RAM (Random Access Memory) or a ROM (Read Only Memory) which demands fast access speed and low power consumption. The ATD detects a variation in an address signal applied from external circuitry and generates a pulse. That is, if there is any variation in address inputs, the ATD generates a clock signal. Furthermore, even if an error in any address input occurs, the ATD receives it, thereby generating a normal internal clock signal.
FIG. 1 shows a schematic block diagram of a semiconductor memory device having an ATD. The semiconductor memory device has an address buffer 100 receiving an external signal, row decoder 200, a memory cell array 300, a column decoder and sense amplifier 400, data output buffer 500, ATD 600 and a pulse generator 700.
The read operation begins with input of wanted address signals into the address buffer. If a transition occurs in one of various input address signals, the ATD 600 senses this occurrence and generates a short pulse. Then the pulse generator 700 generates an ATD pulse such as an equalizing signal EQU, a latch signal LAT, or an inverted latch signal LATB, etc., synchronized with the short pulse.
FIG. 2 to FIG. 5 are disclosed is "IEEE JOURNAL OF SOLID-STATE CIRCUITS," VOL. 24, NO. 5, Oct. 1989, pp. 1250-pp. 1258.
FIG. 2 shows a circuit diagram of a conventional ATD. The ATD generates a short pulse when a transition of an external input address occurs, and a short pulse is generated by a delay circuit 13 (enclosed by a dashed line).
FIG. 3 shows an ATD pulse summator and a pulses generator of FIG. 1. The circuit of FIG. 3 summates the short pulses produced from the ATD to provide desired signals, such as an equalizing signal EQU, an inverted latch signal LATB and a latch signal LAT.
Now, the function of the ATD pulse is described with reference to FIG. 4. The equalizing signal EQU equalizes a bit line and a sense amplifier. The signals LAT and LATB latch valid data and disable or enable a data output buffer. That is, when the signal LAT is of a logic "high", an NMOS transistor 60 is turned on and MOS transistor 63 of an output terminal is enabled.
Next, the read operation of FIG. 4 in normal case is described with reference to FIGS. 3 and 5. When address transition occurs, a word line and a bit line are determined in a row decoder and a column decoder. In this case, signals SATB and SAT indicating the address transition are generated in the ATD, and the equalizing signal EQU synchronized with the signals SATB and SAT is generated in the ATD pulse generator. The equalizing signal EQU performs equalizing operation while the word line and bit line are selected. When the equalizing operation of the equalizing signal EQU is completed, the selected bit line varies in its potential level in response to a state of a cell, and a sense amplifier senses a level of the bit line to produce an amplified signal SA OUTPUT. Meanwhile, the inverted latch signal LATB is disabled to latch read data after the signal SA OUTPUT has changed to a stable level, producing an output signal at an input/output terminal.
When address transition occurs rapidly and is completed in a short time (a few tens of nanoseconds), i.e., during a normal operation, there is no problem in the operation. However, when the address transition occurs slowly and is only completed after a long time (a few milliseconds to a few seconds) on a multiplexed address and data bus, i.e., in the case of address floating, problems may arise. The address floating occurs when the address signal is floated for a long time in order to prevent a bus contention in a memory with a multiplexed address and data bus when the bus switches from data mode into address mode.
A read operation during the address floating is described with reference to FIG. 6. At this time, since the address is slowly changed over a long time, unwanted delay is generated between the output of the address buffer terminal and the output of the ATD for sensing the address transition. Therefore, the ATD and address signals which are intended to be synchronized by an external address signal, are not synchronized. This occurs because the trip level of the address buffer is different from that of the ATD. Accordingly, the signals SATB and SAT for detecting the address transition are firstly generated and the signals EQU and LATB synchronized with the signals SATB and SAT are also generated. Therefore, the equalizing operation and the latch of data are performed before the desired word line and bit line are selected, causing a malfunction which produces incorrect data.